Chips (integrated circuits) form one of the most important hardware foundations of modern information society. A chip is equipped with conductive pins, such as power pins, ground pins and signal pins. A chip is respectively coupled to supply voltage(s) and ground voltage via the power pins and ground pins to drain power for operation. A chip also exchanges signals with other external circuitry (e.g., a circuit board or another chip) via the signal pins.
However, because the power pins, ground pins and signal pins are conductive, external electrical interferences can also be conducted to interior of the chip. EOS is one kind of electric interferences; EOS acts as a high-voltage waveform of considerable time span which propagates from a pin to another pin of a chip, and thus owns great potential to damage the chip.
To address the EOS issue, EOS test is performed for chips. During EOS test, a signal generator provides a waveform to emulate EOS; as two terminals of the signal generator are coupled to two pins of a chip, reaction between the two pins under EOS can be tested. In a chip, since EOS could zap from a signal pin to a ground pin, from a power pin to a signal pin, from a ground pin to a signal pin and from a signal pin to a power pin, EOS test has to cover all these four possible scenarios. However, because a chip has many signal pins and each of the signal pins requires individual test, known prior art has to manually couple the two terminals of the signal generator to associated signal pin, power pin and ground pin, and therefore suffers from time-consuming labor and error-prone issue.